1. Field of the Invention
The present invention relates to an ESD protection circuit, and more particularly, to an ESD protection circuit capable of eliminating gate leakage current.
2. Description of the Prior Art
Please refer to FIG. 1. FIG. 1 shows a simplified block diagram of a conventional ESD protection circuit 100, wherein the ESD protection circuit 100 is an RC-based power-rail ESD clamp circuit. As shown in FIG. 1, the ESD protection circuit 100 comprises: a clamping unit 102, a driving unit 104, a resistance unit 106, and a capacitance unit 110. The clamping device 102 is an N-type metal-oxide-semiconductor (NMOS), and the driving unit 104 is an inverter. Under a normal operation condition, an input terminal of the inverter is at a high voltage level, and thus the output terminal of the inverter is at a low voltage level, and the clamping device 102 (i.e. the NMOS) is turned off. In addition, under an ESD condition, the input terminal of the inverter is initially at a low voltage level comparing with a first power source VDD due to RC time delay generated by the resistance unit 106, and the capacitance unit 110, and thus the output terminal of the inverter will generate a high voltage level to respectively turned on the clamping device 102 (i.e. the NMOS), so as to provide a low impedance path between the first power source VDD and a second power source VSS to eliminate the ESD current.
In addition, please refer to FIG. 2. FIG. 2 shows a simplified block diagram of another conventional ESD protection circuit 200, wherein the ESD protection circuit 200 is a CR-based power-rail ESD clamp circuit. As shown in FIG. 2, the ESD protection circuit 200 comprises: a clamping unit 202, a driving unit 204, a resistance unit 206, and a capacitance unit 210. The clamping device 202 is a P-type metal-oxide-semiconductor (PMOS), and the driving unit 204 is an inverter. Under a normal operation condition, an input terminal of the inverter is at a low voltage level, and thus the output terminal of the inverter is at a high voltage level, and the clamping device 202 (i.e. the PMOS) is turned off. In addition, under an ESD condition, the input terminal of the inverter is initially at a high voltage level comparing with a second power source VSS due to RC time delay generated by the resistance unit 206, and the capacitance unit 210, and thus the output terminal of the inverter will generate a low voltage level to respectively turned on the clamping device 202 (i.e. the PMOS), so as to provide a low impedance path between a first power source VDD and the second power source VSS to eliminate the ESD current.
However, in the advanced CMOS semiconductor process technology, although a metal-oxide-capacitance using a thinner gate oxide layer process requires smaller area, the thinner gate oxide layer will result in larger gate leakage current. Thus, when the capacitance units 110, 210 of the conventional ESD protection circuits 100, 200 are metal-oxide-capacitances with the thin gate oxide layer, the larger gate leakage current generated by the capacitance units 110, 210 may make the conventional ESD protection circuits 100, 200 or other circuits in a chip not able to operate normally.